Rectangular Patch Antenna Residing in a Cavity

This example considers a rectangular patch antenna residing in a cavity.  The example was originally published in [1], which enables an easy comparison of results.  The model is presented in Figure 1.  FEKO offers quite a few options for the simulation of this geometry, with this example highlighting the infinite half-space Green's function and Surface Equivalence Principle (SEP) methods.

Figure 1:  Model of a microstrip patch in a cavity	Dimensions: (patch and cavity centred on origin)
	Patch:   5.0 cm x 3.4 cm (W x H) Cavity:  7.5 cm x 5.1 cm (W x H) Substrate:  εr = 2.17,  tan δ = 0.0015,  h = 0.08779 cm Feed pin:  (1.22, 0.85) cm  =  (xf, yf) Load pin (50 Ω):  (-2.2, -1.5) cm = (xL, yL)

Cavity substrate model options

The patch and cavity walls remain the same, regardless of the simulation technique that is chosen.  These are constructed using metallic rectangles with wire segments connecting the cavity box to the patch at the positions of the feed and load points.  These wire segments may then be used to define the voltage source and load parameters.

Simulation by Infinite Green's Function Planes

The first option for simulation of the substrate is with an infinite half-space Green's function.  The infinite half-space Green's function is placed first and the cavity boundaries are then constructed to have their top edges coincide with the air-dielectric boundary.  The FEKO model for this construction is depicted in Figure 2(a).

Simulation by Surface Equivalence Principle (SEP)

The second option for simulation of the substrate is to use the SEP, constructing a box with dielectric triangles as surfaces to simulate the finite groundplane.  The FEKO model for this construction is depicted in Figure 2(b).

Figure 2:  FEKO models for dielectric substrate in a cavity
(a) Infinite half-space Green's function (b) SEP dielectric surface triangles box

Comparitive Results

The input impedance for the resistively loaded patch was computed with both the Green's function and SEP techniques and the results are presented in Figure 3.  Both results compare favourably with the measured and computed results published in [1, Figure 7].

Figure 3:  Comparitive results: Input impedance of the resistively loaded patch
(a) Real component (b) Imaginary component